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Espressif Systems /ESP32-C6 /TIMG0 /T0CONFIG

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Interpret as T0CONFIG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (USE_XTAL)USE_XTAL 0 (ALARM_EN)ALARM_EN 0 (DIVCNT_RST)DIVCNT_RST 0DIVIDER0 (AUTORELOAD)AUTORELOAD 0 (INCREASE)INCREASE 0 (EN)EN

Description

Timer %s configuration register

Fields

USE_XTAL

1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group.
ALARM_EN

When set, the alarm is enabled. This bit is automatically cleared once an alarm occurs.
DIVCNT_RST

When set, Timer %s 's clock divider counter will be reset.
DIVIDER

Timer %s clock (T%s_clk) prescaler value.
AUTORELOAD

When set, timer %s auto-reload at alarm is enabled.
INCREASE

When set, the timer %s time-base counter will increment every clock tick. When cleared, the timer %s time-base counter will decrement.
EN

When set, the timer %s time-base counter is enabled.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data